The present invention relates to a method of operating a memory device having a multi level cell (MLC). More particularly, the present invention relates to a page buffer for programming the MLC using gray code, a memory device having the page buffer and a method of operating the same.
A well-known NAND flash memory includes a memory cell array, a column decoder, and a page buffer. The memory cell array consists of a plurality of word lines extended along columns, a plurality of bit lines extended along rows and a plurality of cell strings corresponding to the bit lines.
A row decoder connected to a string select line, the word lines and a common source line is located at one side of the memory cell array, and the page buffer connected to the bit lines is located at the other side of the memory cell array.
Multi bit cells for storing a plurality of data bits in one memory cell have been recently developed to enhance the degree of integration of a flash memory. This memory cell is referred to as a multi level cell (hereinafter, referred to as “MLC”). A memory cell for storing one data bit is referred to as a single level cell (SLC).
FIG. 1 is a view illustrating common threshold voltage distribution of MLC for storing 2 data bits.
Referring to FIG. 1, the MLC for storing 2 data bits has four threshold voltage distributions, i.e. threshold voltage distribution [11] not programmed, and threshold voltage distributions [10], [00], and [01] corresponding to a program state.
A program operation includes a least significant bit (LSB) program and a most significant bit MSB program. The LSB program programs [11] state to [10] state in step S101. In addition, the MSB program is performed after the LSB program is performed, and programs [10] state to [00] state in step S102 or programs [11] state to [01] state in step S103.
This program operation programs the MLC using gray code, and changes only one of the bits.
Specifically, in FIG. 1, ‘1’ is changed into ‘0’, i.e. only one bit is changed by one program operation. This program method is applied to the MLC for storing n (an integer) bits as well as two bits. Although an error may occur in one memory cell, the error affects only one of the bits in the memory cell. Thus, the program method uses gray code. Accordingly, memory cells having a threshold voltage of [11] state may be changed to [10] state or [01] state.
A threshold voltage is shifted by Vt1 when [11] state is changed into [10] state, a threshold voltage is shifted by Vt2 when [10] state is changed into [00] state, and a threshold voltage is shifted by Vt3 when [11] state is changed into [01] state. Here, Vt3 is higher than Vt1 and Vt2 as shown in FIG. 1. When the threshold voltage is shifted considerably, an interference effect may occur between the memory cell corresponding to the threshold voltage and an adjacent memory cell. As a result, characteristics of the adjacent memory cell may deteriorate due to the interference effect. In addition, a failure may occur in the memory cell.